Tommaso Apicella

Tommaso Apicella obtained the Master's degree in Electronic Engineering in 2019 from Genoa University, Italy. He is pursuing a PhD in Interactive and Cognitive Environments at the Department of Electrical, Electronic, Telecommunications Engineering and Naval Architecture (DITEN) of the University of Genoa.

His main research areas include: Machine Learning and Pattern Recognition for Embedded Devices.

Additional Info

  • Project title: Machine Learning and Pattern Recognition for Embedded Devices
  • Research project:

    Machine Learning and Deep Learning in particular are playing a key role in the development of ever more intelligent electronic systems. However, the availability of computation resources is a major issue when embedded systems are involved. In general, training is the most computationally hungry process. Nonetheless, even the deployment of the trained model on an embedded system may be a challenging task. In the case of a deep learning architecture, for example, the amount of parameters to be stored in memory can be very large; in addition, the latency of the inference process might not meet real-time requirements.  
    The Ph.D. activity will focus on the design of hardware-friendly paradigms for Machine Learning and Deep Learning. Resource-constrained, battery-operated electronic devices represent the target of the research activity. In principle, the reference scenario is organized as follows: the inference model is hosted on the edge device, while cloud resources are exploited for the training process. Nonetheless, the research activity is expected to also address different scenarios, where training is executed on edge devices as well.
    Computer vision and IoT will provide the application domains. In general, such domains impose quite strict constraints in terms of real-time performances. At the same time, one needs to exploit effective inference models to score high accuracies. Hence, the Ph.D. activity should explore and analyse solutions that can properly balance computational complexity and generalization ability. In this regard, the proposed solutions are expected to effectively leverage existing hardware devices for edge computing, which obviously represent the baseline for this research activity.

  • Primary Supervisor(s): Paolo Gastaldo
  • Secondary Supervisor(s): Andrea Cavallaro
  • PhD cycle: XXXVI